1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device in which passage wirings are arranged above a memory macro, and a layout method thereof. This patent application claims priority based on Japanese patent application No. 2007-0379892. The disclosure of the Japanese patent application is incorporated herein by reference.
2. Description of Related Art
A semiconductor integrated circuit device containing a memory macro has been developed. The memory macro is arranged on a chip. As this memory macro, a DRAM (Dynamic Random Access Memory) macro and an SRAM (Static Random Access Memory) macro are exemplified. In an upper layer of the memory macro, passage wirings are arranged to transmit signals which are not supplied for the memory macro, for convenience of designing. However, depending on the arrangement of the passage wirings, there is a possibility of a malfunction of the memory macro due to noise. Therefore, attention should be paid on the arrangement of the passage wirings.
The memory macro generally includes a memory cell array, an address control circuit, a column peripheral circuit, m word lines, and n digit line pairs. Japanese Patent Application Publication (JP-P2001-156177A) discloses “a library for arrangement and wiring in an integrated circuit and a wiring method”. In this conventional example, the memory cell array is set as a wiring inhibition area, and the passage wirings extending in parallel to the digit line pairs are forbidden from being arranged above the memory cell array. Also, the passage wirings extending in a direction orthogonal to the digit line pairs are restricted in number. Excessive passage wirings are arranged above an area outside the memory macro or above the column peripheral circuit.
The passage wirings provided above the SRAM macro 1 in a direction orthogonal to the digit line pair are permitted since symmetry of the digit lines is not lost. However, the passage wirings provided above the column peripheral circuit in the vertical direction in the orthogonal direction may make the symmetry of the digit lines lost.
FIG. 1 shows a layout of a sense amplifier circuit of the column peripheral circuit as an example. As shown in FIG. 1, in the column peripheral circuit 6, there is a case that a digit line DTj, a transistor Tr1, a digit line DBj, and a transistor Tr2 are not symmetrically arranged for convenience of designing. In this case, the transistors Tr1 and Tr2 are arranged in this order in a direction of the digit lines DTj and DBj, and a passage wiring 120-M is arranged above the transistor Tr1. At this time, it is supposed that noise is generated in the passage wiring 120-M. The noise is generated on the digit line DTj due to a parasitic capacitance between the digit line DTj and the passage wiring 120-M. As the result, the symmetry of the digit lines DTj and DBj is lost. That is to say, since the sense amplifier of the column peripheral circuit is affected by the noise generated on the digit line DTj in detection of a small potential difference between the digit lines DTj and DBj, the entire SRAM macro 1 may malfunction.